1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device.
Though applicable to all semiconductor devices, and specifically to semiconductor devices for power and logic circuits, the present invention and the problems on which it is based are explained with regard to a PMOS transistor for a charge pump circuit in a p-type semiconductor substrate made of silicon.
In the case of customary PMOS transistors using twin CMOS well process technology with an p-type semiconductor substrate, the n-type well in which a transistor is situated cannot be biased negatively with respect to the n-type substrate because an interfering substrate current would flow via a relevant forward-biased pn junction.
The same applies correspondingly in the case of NMOS transistors using triple CMOS well process technologies with a p-type semiconductor substrate, where a further p-type well is additionally provided in the n-type well, or for the respective conductivity types with an n-type semiconductor substrate.
The negative source voltage customarily used in the case of such PMOS transistors effects an increase in the threshold voltage as a result of the so-called substrate control effect.
This effect manifests itself disruptively, for example, in the circuit of the customary charge pump circuit used for the on-chip generation of an increased voltage of, typically, 10 to 15 V from a supply voltage of typically 5 V.
On account of the problems outlined above, the effectiveness of the charge pump circuit diminishes as the threshold voltage of the NMOS transistors provided in a diode connection increases.
In the case of the charge pumps, the increased threshold voltage is intrinsically accepted and specific countermeasures are implemented in order to overcome the problem. In the case of a PMOS charge pump circuit for xe2x88x9212 V, for example, a boost circuit for increasing the gate voltage and also a correspondingly adapted number of pump stages are provided in order to compensate for the reduced effectiveness due to the substrate control of the PMOS transistors. However, solutions of this type are complicated in terms of circuitry.
It is accordingly an object of the invention to provide a method for fabricating a semiconductor device which overcomes the above-mentioned disadvantages of the prior art methods of this general type, in which the substrate control problem is avoided.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor device, including: a semiconductor substrate of a first conductivity type; a first well of a second conductivity type disposed in the semiconductor substrate; a second well of the first conductivity type disposed in the first well; a third well of the second conductivity type disposed in the second well; and a MOS transistor having a source region and a drain region of the first conductivity type, the MOS transistor formed in the third well.
The semiconductor device according to the invention has the advantage over the known solutions in that the substrate control problems can be avoided from the outset by virtue of the fact that the well in which the MOS transistor is located can be biased to the same potential as the source and/or drain terminal of the transistor. The circuitry countermeasures of the prior art can thus be completely omitted.
The idea on which the present invention is based consists in using a quadruple well structure in order to be able to configure the well of the semiconductor device in which the MOS transistor is located such that it can be decoupled from wells located underneath it and to configure a substrate such that it can be decoupled.
According to a preferred embodiment, either the source region or the drain region and also the third well and the second well are connected to receive a first predetermined potential.
According to a further preferred embodiment, the first well and the semiconductor substrate are connected to receive a second predetermined potential.
According to another preferred embodiment, the first conductivity type is p-type and the second conductivity type is n-type.
According to a further preferred embodiment, the first predetermined potential is a negative potential and the second predetermined potential is a ground potential.
According to another preferred embodiment, the first conductivity type is n-type and the second conductivity type is p-type.
According to a further preferred embodiment, the first predetermined potential is a positive potential and the second predetermined potential is a ground potential.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a method for fabricating a semiconductor device, which includes:
implantating and diffusing a first well in a semiconductor substrate; implantating and diffusing a second well in the first well; implantating a third well in the second well; and forming a MOS transistor in the third well.
With the foregoing and other objects in view there is further provided, in accordance with the invention, a charge pump circuit, including: a semiconductor substrate of a first conductivity type; a first well of a second conductivity type disposed in the semiconductor substrate; a second well of the first conductivity type disposed in the first well; a third well of the second conductivity type disposed in the second well; and a MOS transistor having a source region and a drain region of the first conductivity type, the MOS transistor formed in the third well.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a semiconductor device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.